// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC * * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries * * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> * */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mfd/atmel-flexcom.h> #include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/microchip,lan966x.h> / { model = "Microchip LAN966 family SoC"; compatible = "microchip,lan966"; interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; clock-frequency = <600000000>; reg = <0x0>; }; }; clocks { sys_clk: sys_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <165625000>; }; cpu_clk: cpu_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; ddr_clk: ddr_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; nic_clk: nic_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; clks: clock-controller@e00c00a8 { compatible = "microchip,lan966x-gck"; #clock-cells = <1>; clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; clock-names = "cpu", "ddr", "sys"; reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; }; timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <37500000>; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; udc: usb@200000 { compatible = "microchip,lan9662-udc", "atmel,sama5d3-udc"; reg = <0x00200000 0x80000>, <0xe0808000 0x400>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; clock-names = "pclk", "hclk"; status = "disabled"; }; switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; reg = <0xe0000000 0x0100000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "xtr", "fdma", "ana", "ptp", "ptp-ext"; resets = <&reset 0>; reset-names = "switch"; status = "disabled"; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port0: port@0 { reg = <0>; status = "disabled"; }; port1: port@1 { reg = <1>; status = "disabled"; }; port2: port@2 { reg = <2>; status = "disabled"; }; port3: port@3 { reg = <3>; status = "disabled"; }; port4: port@4 { reg = <4>; status = "disabled"; }; port5: port@5 { reg = <5>; status = "disabled"; }; port6: port@6 { reg = <6>; status = "disabled"; }; port7: port@7 { reg = <7>; status = "disabled"; }; }; }; otp: otp@e0021000 { compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc"; reg = <0xe0021000 0x300>; }; flx0: flexcom@e0040000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0040000 0x100>; clocks = <&clks GCK_ID_FLEXCOM0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0040000 0x800>; status = "disabled"; usart0: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, <&dma0 AT91_XDMAC_DT_PERID(2)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi0: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, <&dma0 AT91_XDMAC_DT_PERID(2)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c0: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, <&dma0 AT91_XDMAC_DT_PERID(2)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; flx1: flexcom@e0044000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0044000 0x100>; clocks = <&clks GCK_ID_FLEXCOM1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0044000 0x800>; status = "disabled"; usart1: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, <&dma0 AT91_XDMAC_DT_PERID(4)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi1: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, <&dma0 AT91_XDMAC_DT_PERID(4)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, <&dma0 AT91_XDMAC_DT_PERID(4)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; trng: rng@e0048000 { compatible = "atmel,at91sam9g45-trng"; reg = <0xe0048000 0x100>; clocks = <&nic_clk>; }; aes: crypto@e004c000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xe004c000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, <&dma0 AT91_XDMAC_DT_PERID(13)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "aes_clk"; }; flx2: flexcom@e0060000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0060000 0x100>; clocks = <&clks GCK_ID_FLEXCOM2>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0060000 0x800>; status = "disabled"; usart2: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(6)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi2: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(6)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(6)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; flx3: flexcom@e0064000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0064000 0x100>; clocks = <&clks GCK_ID_FLEXCOM3>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0064000 0x800>; status = "disabled"; usart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi3: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; dma0: dma-controller@e0068000 { compatible = "microchip,sama7g5-dma"; reg = <0xe0068000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; clocks = <&nic_clk>; clock-names = "dma_clk"; }; sha: crypto@e006c000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xe006c000 0xec>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; dma-names = "tx"; clocks = <&nic_clk>; clock-names = "sha_clk"; }; flx4: flexcom@e0070000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0070000 0x100>; clocks = <&clks GCK_ID_FLEXCOM4>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0070000 0x800>; status = "disabled"; usart4: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, <&dma0 AT91_XDMAC_DT_PERID(10)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; status = "disabled"; }; spi4: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, <&dma0 AT91_XDMAC_DT_PERID(10)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "spi_clk"; atmel,fifo-size = <32>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@600 { compatible = "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, <&dma0 AT91_XDMAC_DT_PERID(10)>; dma-names = "tx", "rx"; clocks = <&nic_clk>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; timer0: timer@e008c000 { compatible = "snps,dw-apb-timer"; reg = <0xe008c000 0x400>; clocks = <&nic_clk>; clock-names = "timer"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; }; watchdog: watchdog@e0090000 { compatible = "snps,dw-wdt"; reg = <0xe0090000 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&nic_clk>; status = "disabled"; }; cpu_ctrl: syscon@e00c0000 { compatible = "microchip,lan966x-cpu-syscon", "syscon"; reg = <0xe00c0000 0x350>; }; can0: can@e081c000 { compatible = "bosch,m_can"; reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; clock-names = "hclk", "cclk"; assigned-clocks = <&clks GCK_ID_MCAN0>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; status = "disabled"; }; can1: can@e0820000 { compatible = "bosch,m_can"; reg = <0xe0820000 0xfc>, <0x00100000 0x8000>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>; clock-names = "hclk", "cclk"; assigned-clocks = <&clks GCK_ID_MCAN1>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>; status = "disabled"; }; reset: reset-controller@e200400c { compatible = "microchip,lan966x-switch-reset"; reg = <0xe200400c 0x4>; reg-names = "gcb"; #reset-cells = <1>; cpu-syscon = <&cpu_ctrl>; }; gpio: pinctrl@e2004064 { compatible = "microchip,lan966x-pinctrl"; reg = <0xe2004064 0xb4>, <0xe2010024 0x138>; resets = <&reset 0>; reset-names = "switch"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 78>; interrupt-controller; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; mdio0: mdio@e2004118 { compatible = "microchip,lan966x-miim"; #address-cells = <1>; #size-cells = <0>; reg = <0xe2004118 0x24>; clocks = <&sys_clk>; status = "disabled"; }; mdio1: mdio@e200413c { compatible = "microchip,lan966x-miim"; #address-cells = <1>; #size-cells = <0>; reg = <0xe200413c 0x24>, <0xe2010020 0x4>; clocks = <&sys_clk>; status = "disabled"; phy0: ethernet-phy@1 { reg = <1>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; phy1: ethernet-phy@2 { reg = <2>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; sgpio: gpio@e2004190 { compatible = "microchip,sparx5-sgpio"; reg = <0xe2004190 0x118>; clocks = <&sys_clk>; resets = <&reset 0>; reset-names = "switch"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; sgpio_in: gpio@0 { compatible = "microchip,sparx5-sgpio-bank"; reg = <0>; gpio-controller; #gpio-cells = <3>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>; }; sgpio_out: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; reg = <1>; gpio-controller; #gpio-cells = <3>; }; }; hwmon: hwmon@e2010180 { compatible = "microchip,lan9668-hwmon"; reg = <0xe2010180 0xc>, <0xe20042a8 0xc>; reg-names = "pvt", "fan"; clocks = <&sys_clk>; }; serdes: serdes@e202c000 { compatible = "microchip,lan966x-serdes"; reg = <0xe202c000 0x9c>, <0xe2004010 0x4>; #phy-cells = <2>; status = "disabled"; }; gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; reg = <0xe8c11000 0x1000>, <0xe8c12000 0x2000>, <0xe8c14000 0x2000>, <0xe8c16000 0x2000>; }; }; };