#ifndef ASIC_REG_TPC2_CFG_REGS_H_
#define ASIC_REG_TPC2_CFG_REGS_H_
#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400
#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404
#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408
#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xE86418
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE8641C
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE86420
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xE86424
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86428
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE8642C
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xE86430
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86434
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE86438
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xE8643C
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86440
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86444
#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xE86448
#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE8644C
#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE86450
#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86454
#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86458
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE8645C
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE86460
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xE86464
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86468
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE8646C
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xE86470
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86474
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE86478
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xE8647C
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86480
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86484
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xE86488
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE8648C
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE86490
#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xE86494
#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86498
#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE8649C
#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE864A0
#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE864A4
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE864A8
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE864AC
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xE864B0
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE864B4
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE864B8
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xE864BC
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE864C0
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE864C4
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xE864C8
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE864CC
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE864D0
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xE864D4
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864D8
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864DC
#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xE864E0
#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864E4
#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864E8
#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864EC
#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864F0
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864F4
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864F8
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xE864FC
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE86500
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE86504
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xE86508
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE8650C
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE86510
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xE86514
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE86518
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE8651C
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xE86520
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE86524
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE86528
#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xE8652C
#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE86530
#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE86534
#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE86538
#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE8653C
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE86540
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE86544
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xE86548
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE8654C
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE86550
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xE86554
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86558
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE8655C
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xE86560
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86564
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE86568
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xE8656C
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86570
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86574
#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xE86578
#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE8657C
#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE86580
#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86584
#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86588
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE8658C
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE86590
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xE86594
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86598
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE8659C
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xE865A0
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE865A4
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE865A8
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xE865AC
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE865B0
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE865B4
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xE865B8
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE865BC
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE865C0
#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xE865C4
#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE865C8
#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE865CC
#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE865D0
#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE865D4
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE865D8
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE865DC
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xE865E0
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE865E4
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE865E8
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xE865EC
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE865F0
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE865F4
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xE865F8
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE865FC
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE86600
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xE86604
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86608
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE8660C
#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xE86610
#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86614
#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE86618
#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE8661C
#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86620
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86624
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE86628
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xE8662C
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE86630
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE86634
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xE86638
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE8663C
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE86640
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xE86644
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE86648
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE8664C
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xE86650
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE86654
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE86658
#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xE8665C
#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86660
#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE86664
#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86668
#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE8666C
#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86670
#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE86674
#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE86678
#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE8667C
#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE86680
#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE86684
#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE86688
#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE8668C
#define mmTPC2_CFG_KERNEL_SRF_0 0xE86690
#define mmTPC2_CFG_KERNEL_SRF_1 0xE86694
#define mmTPC2_CFG_KERNEL_SRF_2 0xE86698
#define mmTPC2_CFG_KERNEL_SRF_3 0xE8669C
#define mmTPC2_CFG_KERNEL_SRF_4 0xE866A0
#define mmTPC2_CFG_KERNEL_SRF_5 0xE866A4
#define mmTPC2_CFG_KERNEL_SRF_6 0xE866A8
#define mmTPC2_CFG_KERNEL_SRF_7 0xE866AC
#define mmTPC2_CFG_KERNEL_SRF_8 0xE866B0
#define mmTPC2_CFG_KERNEL_SRF_9 0xE866B4
#define mmTPC2_CFG_KERNEL_SRF_10 0xE866B8
#define mmTPC2_CFG_KERNEL_SRF_11 0xE866BC
#define mmTPC2_CFG_KERNEL_SRF_12 0xE866C0
#define mmTPC2_CFG_KERNEL_SRF_13 0xE866C4
#define mmTPC2_CFG_KERNEL_SRF_14 0xE866C8
#define mmTPC2_CFG_KERNEL_SRF_15 0xE866CC
#define mmTPC2_CFG_KERNEL_SRF_16 0xE866D0
#define mmTPC2_CFG_KERNEL_SRF_17 0xE866D4
#define mmTPC2_CFG_KERNEL_SRF_18 0xE866D8
#define mmTPC2_CFG_KERNEL_SRF_19 0xE866DC
#define mmTPC2_CFG_KERNEL_SRF_20 0xE866E0
#define mmTPC2_CFG_KERNEL_SRF_21 0xE866E4
#define mmTPC2_CFG_KERNEL_SRF_22 0xE866E8
#define mmTPC2_CFG_KERNEL_SRF_23 0xE866EC
#define mmTPC2_CFG_KERNEL_SRF_24 0xE866F0
#define mmTPC2_CFG_KERNEL_SRF_25 0xE866F4
#define mmTPC2_CFG_KERNEL_SRF_26 0xE866F8
#define mmTPC2_CFG_KERNEL_SRF_27 0xE866FC
#define mmTPC2_CFG_KERNEL_SRF_28 0xE86700
#define mmTPC2_CFG_KERNEL_SRF_29 0xE86704
#define mmTPC2_CFG_KERNEL_SRF_30 0xE86708
#define mmTPC2_CFG_KERNEL_SRF_31 0xE8670C
#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE86710
#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86714
#define mmTPC2_CFG_RESERVED_DESC_END 0xE86738
#define mmTPC2_CFG_ROUND_CSR 0xE867FC
#define mmTPC2_CFG_TBUF_BASE_ADDR_LOW 0xE86800
#define mmTPC2_CFG_TBUF_BASE_ADDR_HIGH 0xE86804
#define mmTPC2_CFG_SEMAPHORE 0xE86808
#define mmTPC2_CFG_VFLAGS 0xE8680C
#define mmTPC2_CFG_SFLAGS 0xE86810
#define mmTPC2_CFG_LFSR_POLYNOM 0xE86818
#define mmTPC2_CFG_STATUS 0xE8681C
#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86820
#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86824
#define mmTPC2_CFG_SM_BASE_ADDRESS_LOW 0xE86828
#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8682C
#define mmTPC2_CFG_TPC_CMD 0xE86830
#define mmTPC2_CFG_TPC_EXECUTE 0xE86838
#define mmTPC2_CFG_TPC_STALL 0xE8683C
#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86840
#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86844
#define mmTPC2_CFG_MSS_CONFIG 0xE86854
#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86858
#define mmTPC2_CFG_TPC_INTR_MASK 0xE8685C
#define mmTPC2_CFG_TSB_CONFIG 0xE86860
#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00
#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04
#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08
#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C
#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10
#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14
#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xE86A18
#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A1C
#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A20
#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xE86A24
#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A28
#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A2C
#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xE86A30
#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A34
#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A38
#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xE86A3C
#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A40
#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A44
#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xE86A48
#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A4C
#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A50
#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A54
#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A58
#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A5C
#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A60
#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xE86A64
#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A68
#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A6C
#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xE86A70
#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A74
#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A78
#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xE86A7C
#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A80
#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A84
#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xE86A88
#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A8C
#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A90
#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xE86A94
#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A98
#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A9C
#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86AA0
#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86AA4
#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86AA8
#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86AAC
#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xE86AB0
#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86AB4
#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86AB8
#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xE86ABC
#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86AC0
#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86AC4
#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xE86AC8
#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86ACC
#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86AD0
#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xE86AD4
#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AD8
#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86ADC
#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xE86AE0
#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AE4
#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AE8
#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AEC
#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AF0
#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AF4
#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86AF8
#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xE86AFC
#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86B00
#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86B04
#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xE86B08
#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86B0C
#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86B10
#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xE86B14
#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86B18
#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86B1C
#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xE86B20
#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86B24
#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86B28
#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xE86B2C
#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86B30
#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86B34
#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86B38
#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86B3C
#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86B40
#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86B44
#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xE86B48
#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86B4C
#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86B50
#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xE86B54
#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B58
#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B5C
#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xE86B60
#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B64
#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B68
#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xE86B6C
#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B70
#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B74
#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xE86B78
#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B7C
#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B80
#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B84
#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B88
#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B8C
#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B90
#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xE86B94
#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B98
#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B9C
#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xE86BA0
#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86BA4
#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86BA8
#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xE86BAC
#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86BB0
#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86BB4
#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xE86BB8
#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86BBC
#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86BC0
#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xE86BC4
#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86BC8
#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86BCC
#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86BD0
#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86BD4
#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86BD8
#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86BDC
#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xE86BE0
#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86BE4
#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86BE8
#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xE86BEC
#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86BF0
#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86BF4
#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xE86BF8
#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86BFC
#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86C00
#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xE86C04
#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86C08
#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86C0C
#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xE86C10
#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86C14
#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86C18
#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86C1C
#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86C20
#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86C24
#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86C28
#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xE86C2C
#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86C30
#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86C34
#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xE86C38
#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86C3C
#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86C40
#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xE86C44
#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86C48
#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86C4C
#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xE86C50
#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86C54
#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86C58
#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xE86C5C
#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86C60
#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86C64
#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86C68
#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86C6C
#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86C70
#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86C74
#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86C78
#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86C7C
#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86C80
#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86C84
#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86C88
#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86C8C
#define mmTPC2_CFG_QM_SRF_0 0xE86C90
#define mmTPC2_CFG_QM_SRF_1 0xE86C94
#define mmTPC2_CFG_QM_SRF_2 0xE86C98
#define mmTPC2_CFG_QM_SRF_3 0xE86C9C
#define mmTPC2_CFG_QM_SRF_4 0xE86CA0
#define mmTPC2_CFG_QM_SRF_5 0xE86CA4
#define mmTPC2_CFG_QM_SRF_6 0xE86CA8
#define mmTPC2_CFG_QM_SRF_7 0xE86CAC
#define mmTPC2_CFG_QM_SRF_8 0xE86CB0
#define mmTPC2_CFG_QM_SRF_9 0xE86CB4
#define mmTPC2_CFG_QM_SRF_10 0xE86CB8
#define mmTPC2_CFG_QM_SRF_11 0xE86CBC
#define mmTPC2_CFG_QM_SRF_12 0xE86CC0
#define mmTPC2_CFG_QM_SRF_13 0xE86CC4
#define mmTPC2_CFG_QM_SRF_14 0xE86CC8
#define mmTPC2_CFG_QM_SRF_15 0xE86CCC
#define mmTPC2_CFG_QM_SRF_16 0xE86CD0
#define mmTPC2_CFG_QM_SRF_17 0xE86CD4
#define mmTPC2_CFG_QM_SRF_18 0xE86CD8
#define mmTPC2_CFG_QM_SRF_19 0xE86CDC
#define mmTPC2_CFG_QM_SRF_20 0xE86CE0
#define mmTPC2_CFG_QM_SRF_21 0xE86CE4
#define mmTPC2_CFG_QM_SRF_22 0xE86CE8
#define mmTPC2_CFG_QM_SRF_23 0xE86CEC
#define mmTPC2_CFG_QM_SRF_24 0xE86CF0
#define mmTPC2_CFG_QM_SRF_25 0xE86CF4
#define mmTPC2_CFG_QM_SRF_26 0xE86CF8
#define mmTPC2_CFG_QM_SRF_27 0xE86CFC
#define mmTPC2_CFG_QM_SRF_28 0xE86D00
#define mmTPC2_CFG_QM_SRF_29 0xE86D04
#define mmTPC2_CFG_QM_SRF_30 0xE86D08
#define mmTPC2_CFG_QM_SRF_31 0xE86D0C
#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86D10
#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D14
#define mmTPC2_CFG_ARUSER 0xE86D18
#define mmTPC2_CFG_AWUSER 0xE86D1C
#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE86E00
#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE86E04
#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE86E08
#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE86E0C
#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE86E10
#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE86E14
#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE86E18
#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE86E1C
#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE86E20
#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE86E24
#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE86E28
#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE86E2C
#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */