// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/power/rk3036-power.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rockchip,rk3036";
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
mshc0 = &emmc;
mshc1 = &sdmmc;
mshc2 = &sdio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
spi = &spi;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "rockchip,rk3036-smp";
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
operating-points = <
/* KHz uV */
816000 1000000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x2000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
};
};
gpu: gpu@10090000 {
compatible = "rockchip,rk3036-mali", "arm,mali-400";
reg = <0x10090000 0x10000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0";
assigned-clocks = <&cru SCLK_GPU>;
assigned-clock-rates = <100000000>;
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
clock-names = "bus", "core";
power-domains = <&power RK3036_PD_GPU>;
resets = <&cru SRST_GPU>;
status = "disabled";
};
vpu: video-codec@10108000 {
compatible = "rockchip,rk3036-vpu";
reg = <0x10108000 0x800>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
iommus = <&vpu_mmu>;
power-domains = <&power RK3036_PD_VPU>;
};
vpu_mmu: iommu@10108800 {
compatible = "rockchip,iommu";
reg = <0x10108800 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3036_PD_VPU>;
#iommu-cells = <0>;
};
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
power-domains = <&power RK3036_PD_VIO>;
status = "disabled";
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
};
};
vop_mmu: iommu@10118300 {
compatible = "rockchip,iommu";
reg = <0x10118300 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3036_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
qos_gpu: qos@1012d000 {
compatible = "rockchip,rk3036-qos", "syscon";
reg = <0x1012d000 0x20>;
};
qos_vpu: qos@1012e000 {
compatible = "rockchip,rk3036-qos", "syscon";
reg = <0x1012e000 0x20>;
};
qos_vio: qos@1012f000 {
compatible = "rockchip,rk3036-qos", "syscon";
reg = <0x1012f000 0x20>;
};
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x10139000 0x1000>,
<0x1013a000 0x2000>,
<0x1013c000 0x2000>,
<0x1013e000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
usb_otg: usb@10180000 {
compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG0>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
status = "disabled";
};
usb_host: usb@101c0000 {
compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x101c0000 0x40000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG1>;
clock-names = "otg";
dr_mode = "host";
status = "disabled";
};
emac: ethernet@10200000 {
compatible = "rockchip,rk3036-emac";
reg = <0x10200000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
rockchip,grf = <&grf>;
clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
clock-names = "hclk", "macref", "macclk";
/*
* Fix the emac parent clock is DPLL instead of APLL.
* since that will cause some unstable things if the cpufreq
* is working. (e.g: the accurate 50MHz what mac_ref need)
*/
assigned-clocks = <&cru SCLK_MACPLL>;
assigned-clock-parents = <&cru PLL_DPLL>;
max-speed = <100>;
phy-mode = "rmii";
status = "disabled";
};
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
clock-frequency = <37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_MMC0>;
reset-names = "reset";
status = "disabled";
};
sdio: mmc@10218000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_SDIO>;
reset-names = "reset";
status = "disabled";
};
emmc: mmc@1021c000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
rockchip,default-sample-phase = <158>;
disable-wp;
dmas = <&pdma 12>;
dma-names = "rx-tx";
fifo-depth = <0x100>;
mmc-ddr-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
status = "disabled";
};
i2s: i2s@10220000 {
compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
reg = <0x10220000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
dmas = <&pdma 0>, <&pdma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
nfc: nand-controller@10500000 {
compatible = "rockchip,rk3036-nfc",
"rockchip,rk2928-nfc";
reg = <0x10500000 0x4000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
clock-names = "ahb", "nfc";
assigned-clocks = <&cru SCLK_NANDC>;
assigned-clock-rates = <150000000>;
pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
&flash_rdn &flash_rdy &flash_wrn>;
pinctrl-names = "default";
status = "disabled";
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3036-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <594000000>;
};
grf: syscon@20008000 {
compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
power: power-controller {
compatible = "rockchip,rk3036-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3036_PD_VIO {
reg = <RK3036_PD_VIO>;
clocks = <&cru ACLK_LCDC>,
<&cru HCLK_LCDC>,
<&cru SCLK_LCDC>;
pm_qos = <&qos_vio>;
#power-domain-cells = <0>;
};
power-domain@RK3036_PD_VPU {
reg = <RK3036_PD_VPU>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
};
power-domain@RK3036_PD_GPU {
reg = <RK3036_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x1d8>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
};
};
acodec: acodec-ana@20030000 {
compatible = "rk3036-codec";
reg = <0x20030000 0x4000>;
rockchip,grf = <&grf>;
clock-names = "acodec_pclk";
clocks = <&cru PCLK_ACODEC>;
status = "disabled";
};
hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
status = "disabled";
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_hdmi>;
};
};
};
timer: timer@20044000 {
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
pwm0: pwm@20050000 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
pwm1: pwm@20050010 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
pwm2: pwm@20050020 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
pwm3: pwm@20050030 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};
i2c1: i2c@20056000 {
compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
i2c2: i2c@2005a000 {
compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
reg = <0x2005a000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
uart0: serial@20060000 {
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
reg = <0x20060000 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
};
uart1: serial@20064000 {
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
};
uart2: serial@20068000 {
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
status = "disabled";
};
i2c0: i2c@20072000 {
compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
reg = <0x20072000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
status = "disabled";
};
spi: spi@20074000 {
compatible = "rockchip,rockchip-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
clock-names = "apb-pclk","spi_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pdma: dma-controller@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3036-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_default: pcfg-pull-default {
bias-pull-pin-default;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
};
sdmmc_cd: sdmmc-cd {
rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
<1 RK_PC3 1 &pcfg_pull_default>,
<1 RK_PC4 1 &pcfg_pull_default>,
<1 RK_PC5 1 &pcfg_pull_default>;
};
};
sdio {
sdio_bus1: sdio-bus1 {
rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
<0 RK_PB4 1 &pcfg_pull_default>,
<0 RK_PB5 1 &pcfg_pull_default>,
<0 RK_PB6 1 &pcfg_pull_default>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
};
sdio_clk: sdio-clk {
rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
};
};
emmc {
/*
* We run eMMC at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.
*/
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>,
<1 RK_PD4 2 &pcfg_pull_default>,
<1 RK_PD5 2 &pcfg_pull_default>,
<1 RK_PD6 2 &pcfg_pull_default>,
<1 RK_PD7 2 &pcfg_pull_default>;
};
};
nfc {
flash_ale: flash-ale {
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
};
flash_bus8: flash-bus8 {
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
<1 RK_PD1 1 &pcfg_pull_default>,
<1 RK_PD2 1 &pcfg_pull_default>,
<1 RK_PD3 1 &pcfg_pull_default>,
<1 RK_PD4 1 &pcfg_pull_default>,
<1 RK_PD5 1 &pcfg_pull_default>,
<1 RK_PD6 1 &pcfg_pull_default>,
<1 RK_PD7 1 &pcfg_pull_default>;
};
flash_cle: flash-cle {
rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
};
flash_csn0: flash-csn0 {
rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
};
flash_rdn: flash-rdn {
rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
};
flash_rdy: flash-rdy {
rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
};
flash_wrn: flash-wrn {
rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
};
};
emac {
emac_xfer: emac-xfer {
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
<2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
<2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
<2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
<2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
<2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
<2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
<2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
};
emac_mdio: emac-mdio {
rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
<2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
<0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
<2 RK_PC5 1 &pcfg_pull_none>;
};
};
i2s {
i2s_bus: i2s-bus {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
<1 RK_PA1 1 &pcfg_pull_default>,
<1 RK_PA2 1 &pcfg_pull_default>,
<1 RK_PA3 1 &pcfg_pull_default>,
<1 RK_PA4 1 &pcfg_pull_default>,
<1 RK_PA5 1 &pcfg_pull_default>;
};
};
hdmi {
hdmi_ctl: hdmi-ctl {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
<1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB2 1 &pcfg_pull_none>,
<1 RK_PB3 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
<0 RK_PC1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
<2 RK_PC7 1 &pcfg_pull_none>;
};
/* no rts / cts for uart1 */
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
spi-pins {
spi_txd:spi-txd {
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
};
spi_rxd:spi-rxd {
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
};
spi_clk:spi-clk {
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
};
spi_cs0:spi-cs0 {
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
};
spi_cs1:spi-cs1 {
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
};
};
};
};