#ifndef ASIC_REG_DCORE0_MME_QM_REGS_H_
#define ASIC_REG_DCORE0_MME_QM_REGS_H_
#define mmDCORE0_MME_QM_GLBL_CFG0 0x40CA000
#define mmDCORE0_MME_QM_GLBL_CFG1 0x40CA004
#define mmDCORE0_MME_QM_GLBL_CFG2 0x40CA008
#define mmDCORE0_MME_QM_GLBL_ERR_CFG 0x40CA00C
#define mmDCORE0_MME_QM_GLBL_ERR_CFG1 0x40CA010
#define mmDCORE0_MME_QM_GLBL_ERR_ARC_HALT_EN 0x40CA014
#define mmDCORE0_MME_QM_GLBL_AXCACHE 0x40CA018
#define mmDCORE0_MME_QM_GLBL_STS0 0x40CA01C
#define mmDCORE0_MME_QM_GLBL_STS1 0x40CA020
#define mmDCORE0_MME_QM_GLBL_ERR_STS_0 0x40CA024
#define mmDCORE0_MME_QM_GLBL_ERR_STS_1 0x40CA028
#define mmDCORE0_MME_QM_GLBL_ERR_STS_2 0x40CA02C
#define mmDCORE0_MME_QM_GLBL_ERR_STS_3 0x40CA030
#define mmDCORE0_MME_QM_GLBL_ERR_STS_4 0x40CA034
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_0 0x40CA038
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_1 0x40CA03C
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_2 0x40CA040
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_3 0x40CA044
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_4 0x40CA048
#define mmDCORE0_MME_QM_GLBL_PROT 0x40CA04C
#define mmDCORE0_MME_QM_PQ_BASE_LO_0 0x40CA050
#define mmDCORE0_MME_QM_PQ_BASE_LO_1 0x40CA054
#define mmDCORE0_MME_QM_PQ_BASE_LO_2 0x40CA058
#define mmDCORE0_MME_QM_PQ_BASE_LO_3 0x40CA05C
#define mmDCORE0_MME_QM_PQ_BASE_HI_0 0x40CA060
#define mmDCORE0_MME_QM_PQ_BASE_HI_1 0x40CA064
#define mmDCORE0_MME_QM_PQ_BASE_HI_2 0x40CA068
#define mmDCORE0_MME_QM_PQ_BASE_HI_3 0x40CA06C
#define mmDCORE0_MME_QM_PQ_SIZE_0 0x40CA070
#define mmDCORE0_MME_QM_PQ_SIZE_1 0x40CA074
#define mmDCORE0_MME_QM_PQ_SIZE_2 0x40CA078
#define mmDCORE0_MME_QM_PQ_SIZE_3 0x40CA07C
#define mmDCORE0_MME_QM_PQ_PI_0 0x40CA080
#define mmDCORE0_MME_QM_PQ_PI_1 0x40CA084
#define mmDCORE0_MME_QM_PQ_PI_2 0x40CA088
#define mmDCORE0_MME_QM_PQ_PI_3 0x40CA08C
#define mmDCORE0_MME_QM_PQ_CI_0 0x40CA090
#define mmDCORE0_MME_QM_PQ_CI_1 0x40CA094
#define mmDCORE0_MME_QM_PQ_CI_2 0x40CA098
#define mmDCORE0_MME_QM_PQ_CI_3 0x40CA09C
#define mmDCORE0_MME_QM_PQ_CFG0_0 0x40CA0A0
#define mmDCORE0_MME_QM_PQ_CFG0_1 0x40CA0A4
#define mmDCORE0_MME_QM_PQ_CFG0_2 0x40CA0A8
#define mmDCORE0_MME_QM_PQ_CFG0_3 0x40CA0AC
#define mmDCORE0_MME_QM_PQ_CFG1_0 0x40CA0B0
#define mmDCORE0_MME_QM_PQ_CFG1_1 0x40CA0B4
#define mmDCORE0_MME_QM_PQ_CFG1_2 0x40CA0B8
#define mmDCORE0_MME_QM_PQ_CFG1_3 0x40CA0BC
#define mmDCORE0_MME_QM_PQ_STS0_0 0x40CA0C0
#define mmDCORE0_MME_QM_PQ_STS0_1 0x40CA0C4
#define mmDCORE0_MME_QM_PQ_STS0_2 0x40CA0C8
#define mmDCORE0_MME_QM_PQ_STS0_3 0x40CA0CC
#define mmDCORE0_MME_QM_PQ_STS1_0 0x40CA0D0
#define mmDCORE0_MME_QM_PQ_STS1_1 0x40CA0D4
#define mmDCORE0_MME_QM_PQ_STS1_2 0x40CA0D8
#define mmDCORE0_MME_QM_PQ_STS1_3 0x40CA0DC
#define mmDCORE0_MME_QM_CQ_CFG0_0 0x40CA0E0
#define mmDCORE0_MME_QM_CQ_CFG0_1 0x40CA0E4
#define mmDCORE0_MME_QM_CQ_CFG0_2 0x40CA0E8
#define mmDCORE0_MME_QM_CQ_CFG0_3 0x40CA0EC
#define mmDCORE0_MME_QM_CQ_CFG0_4 0x40CA0F0
#define mmDCORE0_MME_QM_CQ_STS0_0 0x40CA0F4
#define mmDCORE0_MME_QM_CQ_STS0_1 0x40CA0F8
#define mmDCORE0_MME_QM_CQ_STS0_2 0x40CA0FC
#define mmDCORE0_MME_QM_CQ_STS0_3 0x40CA100
#define mmDCORE0_MME_QM_CQ_STS0_4 0x40CA104
#define mmDCORE0_MME_QM_CQ_CFG1_0 0x40CA108
#define mmDCORE0_MME_QM_CQ_CFG1_1 0x40CA10C
#define mmDCORE0_MME_QM_CQ_CFG1_2 0x40CA110
#define mmDCORE0_MME_QM_CQ_CFG1_3 0x40CA114
#define mmDCORE0_MME_QM_CQ_CFG1_4 0x40CA118
#define mmDCORE0_MME_QM_CQ_STS1_0 0x40CA11C
#define mmDCORE0_MME_QM_CQ_STS1_1 0x40CA120
#define mmDCORE0_MME_QM_CQ_STS1_2 0x40CA124
#define mmDCORE0_MME_QM_CQ_STS1_3 0x40CA128
#define mmDCORE0_MME_QM_CQ_STS1_4 0x40CA12C
#define mmDCORE0_MME_QM_CQ_PTR_LO_0 0x40CA150
#define mmDCORE0_MME_QM_CQ_PTR_HI_0 0x40CA154
#define mmDCORE0_MME_QM_CQ_TSIZE_0 0x40CA158
#define mmDCORE0_MME_QM_CQ_CTL_0 0x40CA15C
#define mmDCORE0_MME_QM_CQ_PTR_LO_1 0x40CA160
#define mmDCORE0_MME_QM_CQ_PTR_HI_1 0x40CA164
#define mmDCORE0_MME_QM_CQ_TSIZE_1 0x40CA168
#define mmDCORE0_MME_QM_CQ_CTL_1 0x40CA16C
#define mmDCORE0_MME_QM_CQ_PTR_LO_2 0x40CA170
#define mmDCORE0_MME_QM_CQ_PTR_HI_2 0x40CA174
#define mmDCORE0_MME_QM_CQ_TSIZE_2 0x40CA178
#define mmDCORE0_MME_QM_CQ_CTL_2 0x40CA17C
#define mmDCORE0_MME_QM_CQ_PTR_LO_3 0x40CA180
#define mmDCORE0_MME_QM_CQ_PTR_HI_3 0x40CA184
#define mmDCORE0_MME_QM_CQ_TSIZE_3 0x40CA188
#define mmDCORE0_MME_QM_CQ_CTL_3 0x40CA18C
#define mmDCORE0_MME_QM_CQ_PTR_LO_4 0x40CA190
#define mmDCORE0_MME_QM_CQ_PTR_HI_4 0x40CA194
#define mmDCORE0_MME_QM_CQ_TSIZE_4 0x40CA198
#define mmDCORE0_MME_QM_CQ_CTL_4 0x40CA19C
#define mmDCORE0_MME_QM_CQ_TSIZE_STS_0 0x40CA1A0
#define mmDCORE0_MME_QM_CQ_TSIZE_STS_1 0x40CA1A4
#define mmDCORE0_MME_QM_CQ_TSIZE_STS_2 0x40CA1A8
#define mmDCORE0_MME_QM_CQ_TSIZE_STS_3 0x40CA1AC
#define mmDCORE0_MME_QM_CQ_TSIZE_STS_4 0x40CA1B0
#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_0 0x40CA1B4
#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_1 0x40CA1B8
#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_2 0x40CA1BC
#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_3 0x40CA1C0
#define mmDCORE0_MME_QM_CQ_PTR_LO_STS_4 0x40CA1C4
#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_0 0x40CA1C8
#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_1 0x40CA1CC
#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_2 0x40CA1D0
#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_3 0x40CA1D4
#define mmDCORE0_MME_QM_CQ_PTR_HI_STS_4 0x40CA1D8
#define mmDCORE0_MME_QM_CQ_IFIFO_STS_0 0x40CA1DC
#define mmDCORE0_MME_QM_CQ_IFIFO_STS_1 0x40CA1E0
#define mmDCORE0_MME_QM_CQ_IFIFO_STS_2 0x40CA1E4
#define mmDCORE0_MME_QM_CQ_IFIFO_STS_3 0x40CA1E8
#define mmDCORE0_MME_QM_CQ_IFIFO_STS_4 0x40CA1EC
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0 0x40CA1F0
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1 0x40CA1F4
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2 0x40CA1F8
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3 0x40CA1FC
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4 0x40CA200
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0 0x40CA204
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1 0x40CA208
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2 0x40CA20C
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3 0x40CA210
#define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4 0x40CA214
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0 0x40CA218
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1 0x40CA21C
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2 0x40CA220
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3 0x40CA224
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4 0x40CA228
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0 0x40CA22C
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1 0x40CA230
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2 0x40CA234
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3 0x40CA238
#define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4 0x40CA23C
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0 0x40CA240
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1 0x40CA244
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2 0x40CA248
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3 0x40CA24C
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4 0x40CA250
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0 0x40CA254
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1 0x40CA258
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2 0x40CA25C
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3 0x40CA260
#define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4 0x40CA264
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0 0x40CA268
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1 0x40CA26C
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2 0x40CA270
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3 0x40CA274
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4 0x40CA278
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0 0x40CA27C
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1 0x40CA280
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2 0x40CA284
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3 0x40CA288
#define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4 0x40CA28C
#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_0 0x40CA290
#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_1 0x40CA294
#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_2 0x40CA298
#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_3 0x40CA29C
#define mmDCORE0_MME_QM_CP_FENCE0_RDATA_4 0x40CA2A0
#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_0 0x40CA2A4
#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_1 0x40CA2A8
#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_2 0x40CA2AC
#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_3 0x40CA2B0
#define mmDCORE0_MME_QM_CP_FENCE1_RDATA_4 0x40CA2B4
#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_0 0x40CA2B8
#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_1 0x40CA2BC
#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_2 0x40CA2C0
#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_3 0x40CA2C4
#define mmDCORE0_MME_QM_CP_FENCE2_RDATA_4 0x40CA2C8
#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_0 0x40CA2CC
#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_1 0x40CA2D0
#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_2 0x40CA2D4
#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_3 0x40CA2D8
#define mmDCORE0_MME_QM_CP_FENCE3_RDATA_4 0x40CA2DC
#define mmDCORE0_MME_QM_CP_FENCE0_CNT_0 0x40CA2E0
#define mmDCORE0_MME_QM_CP_FENCE0_CNT_1 0x40CA2E4
#define mmDCORE0_MME_QM_CP_FENCE0_CNT_2 0x40CA2E8
#define mmDCORE0_MME_QM_CP_FENCE0_CNT_3 0x40CA2EC
#define mmDCORE0_MME_QM_CP_FENCE0_CNT_4 0x40CA2F0
#define mmDCORE0_MME_QM_CP_FENCE1_CNT_0 0x40CA2F4
#define mmDCORE0_MME_QM_CP_FENCE1_CNT_1 0x40CA2F8
#define mmDCORE0_MME_QM_CP_FENCE1_CNT_2 0x40CA2FC
#define mmDCORE0_MME_QM_CP_FENCE1_CNT_3 0x40CA300
#define mmDCORE0_MME_QM_CP_FENCE1_CNT_4 0x40CA304
#define mmDCORE0_MME_QM_CP_FENCE2_CNT_0 0x40CA308
#define mmDCORE0_MME_QM_CP_FENCE2_CNT_1 0x40CA30C
#define mmDCORE0_MME_QM_CP_FENCE2_CNT_2 0x40CA310
#define mmDCORE0_MME_QM_CP_FENCE2_CNT_3 0x40CA314
#define mmDCORE0_MME_QM_CP_FENCE2_CNT_4 0x40CA318
#define mmDCORE0_MME_QM_CP_FENCE3_CNT_0 0x40CA31C
#define mmDCORE0_MME_QM_CP_FENCE3_CNT_1 0x40CA320
#define mmDCORE0_MME_QM_CP_FENCE3_CNT_2 0x40CA324
#define mmDCORE0_MME_QM_CP_FENCE3_CNT_3 0x40CA328
#define mmDCORE0_MME_QM_CP_FENCE3_CNT_4 0x40CA32C
#define mmDCORE0_MME_QM_CP_BARRIER_CFG 0x40CA330
#define mmDCORE0_MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x40CA334
#define mmDCORE0_MME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x40CA338
#define mmDCORE0_MME_QM_CP_LDMA_TSIZE_OFFSET 0x40CA33C
#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_0 0x40CA340
#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_1 0x40CA344
#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_2 0x40CA348
#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_3 0x40CA34C
#define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_4 0x40CA350
#define mmDCORE0_MME_QM_CP_STS_0 0x40CA368
#define mmDCORE0_MME_QM_CP_STS_1 0x40CA36C
#define mmDCORE0_MME_QM_CP_STS_2 0x40CA370
#define mmDCORE0_MME_QM_CP_STS_3 0x40CA374
#define mmDCORE0_MME_QM_CP_STS_4 0x40CA378
#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_0 0x40CA37C
#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_1 0x40CA380
#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_2 0x40CA384
#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_3 0x40CA388
#define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_4 0x40CA38C
#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_0 0x40CA390
#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_1 0x40CA394
#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_2 0x40CA398
#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_3 0x40CA39C
#define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_4 0x40CA3A0
#define mmDCORE0_MME_QM_CP_PRED_0 0x40CA3A4
#define mmDCORE0_MME_QM_CP_PRED_1 0x40CA3A8
#define mmDCORE0_MME_QM_CP_PRED_2 0x40CA3AC
#define mmDCORE0_MME_QM_CP_PRED_3 0x40CA3B0
#define mmDCORE0_MME_QM_CP_PRED_4 0x40CA3B4
#define mmDCORE0_MME_QM_CP_PRED_UPEN_0 0x40CA3B8
#define mmDCORE0_MME_QM_CP_PRED_UPEN_1 0x40CA3BC
#define mmDCORE0_MME_QM_CP_PRED_UPEN_2 0x40CA3C0
#define mmDCORE0_MME_QM_CP_PRED_UPEN_3 0x40CA3C4
#define mmDCORE0_MME_QM_CP_PRED_UPEN_4 0x40CA3C8
#define mmDCORE0_MME_QM_CP_DBG_0_0 0x40CA3CC
#define mmDCORE0_MME_QM_CP_DBG_0_1 0x40CA3D0
#define mmDCORE0_MME_QM_CP_DBG_0_2 0x40CA3D4
#define mmDCORE0_MME_QM_CP_DBG_0_3 0x40CA3D8
#define mmDCORE0_MME_QM_CP_DBG_0_4 0x40CA3DC
#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_0 0x40CA3E0
#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_1 0x40CA3E4
#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_2 0x40CA3E8
#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_3 0x40CA3EC
#define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_4 0x40CA3F0
#define mmDCORE0_MME_QM_CP_IN_DATA_LO_0 0x40CA3F4
#define mmDCORE0_MME_QM_CP_IN_DATA_LO_1 0x40CA3F8
#define mmDCORE0_MME_QM_CP_IN_DATA_LO_2 0x40CA3FC
#define mmDCORE0_MME_QM_CP_IN_DATA_LO_3 0x40CA400
#define mmDCORE0_MME_QM_CP_IN_DATA_LO_4 0x40CA404
#define mmDCORE0_MME_QM_CP_IN_DATA_HI_0 0x40CA408
#define mmDCORE0_MME_QM_CP_IN_DATA_HI_1 0x40CA40C
#define mmDCORE0_MME_QM_CP_IN_DATA_HI_2 0x40CA410
#define mmDCORE0_MME_QM_CP_IN_DATA_HI_3 0x40CA414
#define mmDCORE0_MME_QM_CP_IN_DATA_HI_4 0x40CA418
#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_0 0x40CA41C
#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_1 0x40CA420
#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_2 0x40CA424
#define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_3 0x40CA428
#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_0 0x40CA42C
#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_1 0x40CA430
#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_2 0x40CA434
#define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_3 0x40CA438
#define mmDCORE0_MME_QM_PQC_SIZE_0 0x40CA43C
#define mmDCORE0_MME_QM_PQC_SIZE_1 0x40CA440
#define mmDCORE0_MME_QM_PQC_SIZE_2 0x40CA444
#define mmDCORE0_MME_QM_PQC_SIZE_3 0x40CA448
#define mmDCORE0_MME_QM_PQC_PI_0 0x40CA44C
#define mmDCORE0_MME_QM_PQC_PI_1 0x40CA450
#define mmDCORE0_MME_QM_PQC_PI_2 0x40CA454
#define mmDCORE0_MME_QM_PQC_PI_3 0x40CA458
#define mmDCORE0_MME_QM_PQC_LBW_WDATA_0 0x40CA45C
#define mmDCORE0_MME_QM_PQC_LBW_WDATA_1 0x40CA460
#define mmDCORE0_MME_QM_PQC_LBW_WDATA_2 0x40CA464
#define mmDCORE0_MME_QM_PQC_LBW_WDATA_3 0x40CA468
#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_0 0x40CA46C
#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_1 0x40CA470
#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_2 0x40CA474
#define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_3 0x40CA478
#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_0 0x40CA47C
#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_1 0x40CA480
#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_2 0x40CA484
#define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_3 0x40CA488
#define mmDCORE0_MME_QM_PQC_CFG 0x40CA48C
#define mmDCORE0_MME_QM_PQC_SECURE_PUSH_IND 0x40CA490
#define mmDCORE0_MME_QM_ARB_MASK 0x40CA4A0
#define mmDCORE0_MME_QM_ARB_CFG_0 0x40CA4A4
#define mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH 0x40CA4A8
#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0 0x40CA4AC
#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1 0x40CA4B0
#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2 0x40CA4B4
#define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3 0x40CA4B8
#define mmDCORE0_MME_QM_ARB_CFG_1 0x40CA4BC
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_0 0x40CA4C0
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_1 0x40CA4C4
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_2 0x40CA4C8
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_3 0x40CA4CC
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_4 0x40CA4D0
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_5 0x40CA4D4
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_6 0x40CA4D8
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_7 0x40CA4DC
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_8 0x40CA4E0
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_9 0x40CA4E4
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_10 0x40CA4E8
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_11 0x40CA4EC
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_12 0x40CA4F0
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_13 0x40CA4F4
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_14 0x40CA4F8
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_15 0x40CA4FC
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_16 0x40CA500
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_17 0x40CA504
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_18 0x40CA508
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_19 0x40CA50C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_20 0x40CA510
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_21 0x40CA514
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_22 0x40CA518
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_23 0x40CA51C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_24 0x40CA520
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_25 0x40CA524
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_26 0x40CA528
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_27 0x40CA52C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_28 0x40CA530
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_29 0x40CA534
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_30 0x40CA538
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_31 0x40CA53C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_32 0x40CA540
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_33 0x40CA544
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_34 0x40CA548
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_35 0x40CA54C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_36 0x40CA550
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_37 0x40CA554
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_38 0x40CA558
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_39 0x40CA55C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_40 0x40CA560
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_41 0x40CA564
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_42 0x40CA568
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_43 0x40CA56C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_44 0x40CA570
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_45 0x40CA574
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_46 0x40CA578
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_47 0x40CA57C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_48 0x40CA580
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_49 0x40CA584
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_50 0x40CA588
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_51 0x40CA58C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_52 0x40CA590
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_53 0x40CA594
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_54 0x40CA598
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_55 0x40CA59C
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_56 0x40CA5A0
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_57 0x40CA5A4
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_58 0x40CA5A8
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_59 0x40CA5AC
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_60 0x40CA5B0
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_61 0x40CA5B4
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_62 0x40CA5B8
#define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_63 0x40CA5BC
#define mmDCORE0_MME_QM_ARB_MST_CRED_INC 0x40CA5E0
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x40CA5E4
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x40CA5E8
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x40CA5EC
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x40CA5F0
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x40CA5F4
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x40CA5F8
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x40CA5FC
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x40CA600
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x40CA604
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x40CA608
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x40CA60C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x40CA610
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x40CA614
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x40CA618
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x40CA61C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x40CA620
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x40CA624
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x40CA628
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x40CA62C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x40CA630
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x40CA634
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x40CA638
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x40CA63C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x40CA640
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x40CA644
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x40CA648
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x40CA64C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x40CA650
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x40CA654
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x40CA658
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x40CA65C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x40CA660
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x40CA664
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x40CA668
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x40CA66C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x40CA670
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x40CA674
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x40CA678
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x40CA67C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x40CA680
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x40CA684
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x40CA688
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x40CA68C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x40CA690
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x40CA694
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x40CA698
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x40CA69C
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x40CA6A0
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x40CA6A4
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x40CA6A8
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x40CA6AC
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x40CA6B0
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x40CA6B4
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x40CA6B8
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x40CA6BC
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x40CA6C0
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x40CA6C4
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x40CA6C8
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x40CA6CC
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x40CA6D0
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x40CA6D4
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x40CA6D8
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x40CA6DC
#define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x40CA6E0
#define mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x40CA704
#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN 0x40CA708
#define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1 0x40CA70C
#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_WDT 0x40CA710
#define mmDCORE0_MME_QM_ARB_SLV_ID 0x40CA714
#define mmDCORE0_MME_QM_ARB_MST_QUIET_PER 0x40CA718
#define mmDCORE0_MME_QM_ARB_MSG_MAX_INFLIGHT 0x40CA744
#define mmDCORE0_MME_QM_ARB_BASE_LO 0x40CA754
#define mmDCORE0_MME_QM_ARB_BASE_HI 0x40CA758
#define mmDCORE0_MME_QM_ARB_STATE_STS 0x40CA780
#define mmDCORE0_MME_QM_ARB_CHOICE_FULLNESS_STS 0x40CA784
#define mmDCORE0_MME_QM_ARB_MSG_STS 0x40CA788
#define mmDCORE0_MME_QM_ARB_SLV_CHOICE_Q_HEAD 0x40CA78C
#define mmDCORE0_MME_QM_ARB_ERR_CAUSE 0x40CA79C
#define mmDCORE0_MME_QM_ARB_ERR_MSG_EN 0x40CA7A0
#define mmDCORE0_MME_QM_ARB_ERR_STS_DRP 0x40CA7A8
#define mmDCORE0_MME_QM_ARB_MST_CRED_STS 0x40CA7B0
#define mmDCORE0_MME_QM_ARB_MST_CRED_STS_1 0x40CA7B4
#define mmDCORE0_MME_QM_CSMR_STRICT_PRIO_CFG 0x40CA7FC
#define mmDCORE0_MME_QM_ARC_CQ_CFG0 0x40CA800
#define mmDCORE0_MME_QM_ARC_CQ_CFG1 0x40CA804
#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO 0x40CA808
#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI 0x40CA80C
#define mmDCORE0_MME_QM_ARC_CQ_TSIZE 0x40CA810
#define mmDCORE0_MME_QM_ARC_CQ_CTL 0x40CA814
#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_STS 0x40CA81C
#define mmDCORE0_MME_QM_ARC_CQ_STS0 0x40CA820
#define mmDCORE0_MME_QM_ARC_CQ_STS1 0x40CA824
#define mmDCORE0_MME_QM_ARC_CQ_TSIZE_STS 0x40CA828
#define mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS 0x40CA82C
#define mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS 0x40CA830
#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_HI 0x40CA834
#define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_LO 0x40CA838
#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x40CA83C
#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x40CA840
#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_HI 0x40CA844
#define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO 0x40CA848
#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_HI 0x40CA84C
#define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO 0x40CA850
#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_HI 0x40CA854
#define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO 0x40CA858
#define mmDCORE0_MME_QM_ADDR_OVRD 0x40CA85C
#define mmDCORE0_MME_QM_CQ_IFIFO_CI_0 0x40CA860
#define mmDCORE0_MME_QM_CQ_IFIFO_CI_1 0x40CA864
#define mmDCORE0_MME_QM_CQ_IFIFO_CI_2 0x40CA868
#define mmDCORE0_MME_QM_CQ_IFIFO_CI_3 0x40CA86C
#define mmDCORE0_MME_QM_CQ_IFIFO_CI_4 0x40CA870
#define mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI 0x40CA874
#define mmDCORE0_MME_QM_CQ_CTL_CI_0 0x40CA878
#define mmDCORE0_MME_QM_CQ_CTL_CI_1 0x40CA87C
#define mmDCORE0_MME_QM_CQ_CTL_CI_2 0x40CA880
#define mmDCORE0_MME_QM_CQ_CTL_CI_3 0x40CA884
#define mmDCORE0_MME_QM_CQ_CTL_CI_4 0x40CA888
#define mmDCORE0_MME_QM_ARC_CQ_CTL_CI 0x40CA88C
#define mmDCORE0_MME_QM_CP_CFG 0x40CA890
#define mmDCORE0_MME_QM_CP_EXT_SWITCH 0x40CA894
#define mmDCORE0_MME_QM_CP_SWITCH_WD_SET 0x40CA898
#define mmDCORE0_MME_QM_CP_SWITCH_WD 0x40CA89C
#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_LO 0x40CA8A4
#define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_HI 0x40CA8A8
#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_HI 0x40CA8AC
#define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_LO 0x40CA8B0
#define mmDCORE0_MME_QM_ENGINE_ADDR_RANGE_SIZE 0x40CA8B4
#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_HI 0x40CA8B8
#define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_LO 0x40CA8BC
#define mmDCORE0_MME_QM_QM_BASE_ADDR_HI 0x40CA8C0
#define mmDCORE0_MME_QM_QM_BASE_ADDR_LO 0x40CA8C4
#define mmDCORE0_MME_QM_ARC_PQC_SECURE_PUSH_IND 0x40CA8C8
#define mmDCORE0_MME_QM_PQC_STS_0_0 0x40CA8D0
#define mmDCORE0_MME_QM_PQC_STS_0_1 0x40CA8D4
#define mmDCORE0_MME_QM_PQC_STS_0_2 0x40CA8D8
#define mmDCORE0_MME_QM_PQC_STS_0_3 0x40CA8DC
#define mmDCORE0_MME_QM_PQC_STS_1_0 0x40CA8E0
#define mmDCORE0_MME_QM_PQC_STS_1_1 0x40CA8E4
#define mmDCORE0_MME_QM_PQC_STS_1_2 0x40CA8E8
#define mmDCORE0_MME_QM_PQC_STS_1_3 0x40CA8EC
#define mmDCORE0_MME_QM_SEI_STATUS 0x40CA8F0
#define mmDCORE0_MME_QM_SEI_MASK 0x40CA8F4
#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_LO 0x40CAD00
#define mmDCORE0_MME_QM_GLBL_ERR_ADDR_HI 0x40CAD04
#define mmDCORE0_MME_QM_GLBL_ERR_WDATA 0x40CAD08
#define mmDCORE0_MME_QM_L2H_MASK_LO 0x40CAD14
#define mmDCORE0_MME_QM_L2H_MASK_HI 0x40CAD18
#define mmDCORE0_MME_QM_L2H_CMPR_LO 0x40CAD1C
#define mmDCORE0_MME_QM_L2H_CMPR_HI 0x40CAD20
#define mmDCORE0_MME_QM_LOCAL_RANGE_BASE 0x40CAD24
#define mmDCORE0_MME_QM_LOCAL_RANGE_SIZE 0x40CAD28
#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_1 0x40CAD30
#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_0 0x40CAD34
#define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_1 0x40CAD38
#define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_0 0x40CAD3C
#define mmDCORE0_MME_QM_IND_GW_APB_CFG 0x40CAD40
#define mmDCORE0_MME_QM_IND_GW_APB_WDATA 0x40CAD44
#define mmDCORE0_MME_QM_IND_GW_APB_RDATA 0x40CAD48
#define mmDCORE0_MME_QM_IND_GW_APB_STATUS 0x40CAD4C
#define mmDCORE0_MME_QM_PERF_CNT_FREE_LO 0x40CAD60
#define mmDCORE0_MME_QM_PERF_CNT_FREE_HI 0x40CAD64
#define mmDCORE0_MME_QM_PERF_CNT_IDLE_LO 0x40CAD68
#define mmDCORE0_MME_QM_PERF_CNT_IDLE_HI 0x40CAD6C
#define mmDCORE0_MME_QM_PERF_CNT_CFG 0x40CAD70
#endif /* ASIC_REG_DCORE0_MME_QM_REGS_H_ */