# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright (c) 2020 MediaTek %YAML 1.2 --- $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek High Definition Multimedia Interface (HDMI) PHY maintainers: - Chun-Kuang Hu <chunkuang.hu@kernel.org> - Philipp Zabel <p.zabel@pengutronix.de> - Chunfeng Yun <chunfeng.yun@mediatek.com> description: | The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel output and drives the HDMI pads. properties: $nodename: pattern: "^hdmi-phy@[0-9a-f]+$" compatible: oneOf: - items: - enum: - mediatek,mt7623-hdmi-phy - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt8173-hdmi-phy - const: mediatek,mt8195-hdmi-phy reg: maxItems: 1 clocks: items: - description: PLL reference clock clock-names: items: - const: pll_ref clock-output-names: items: - const: hdmitx_dig_cts "#phy-cells": const: 0 "#clock-cells": const: 0 mediatek,ibias: description: TX DRV bias current for < 1.65Gbps $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 63 default: 0xa mediatek,ibias_up: description: TX DRV bias current for >= 1.65Gbps $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 63 default: 0x1c required: - compatible - reg - clocks - clock-names - clock-output-names - "#phy-cells" - "#clock-cells" additionalProperties: false examples: - | #include <dt-bindings/clock/mt8173-clk.h> hdmi_phy: hdmi-phy@10209100 { compatible = "mediatek,mt8173-hdmi-phy"; reg = <0x10209100 0x24>; clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; clock-names = "pll_ref"; clock-output-names = "hdmitx_dig_cts"; mediatek,ibias = <0xa>; mediatek,ibias_up = <0x1c>; #clock-cells = <0>; #phy-cells = <0>; }; ...