// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Amazon's Annapurna Labs Alpine v3";
compatible = "amazon,al-alpine-v3";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster0_l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x1>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster0_l2>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x2>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster0_l2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x3>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster0_l2>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster1_l2>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster1_l2>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x102>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster1_l2>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x103>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster1_l2>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster2_l2>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x201>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster2_l2>;
};
cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x202>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster2_l2>;
};
cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x203>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster2_l2>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x300>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster3_l2>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x301>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster3_l2>;
};
cpu@302 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x302>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster3_l2>;
};
cpu@303 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x303>;
enable-method = "psci";
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: cache@0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
cluster1_l2: cache@100 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
cluster2_l2: cache@200 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
cluster3_l2: cache@300 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secmon@0 {
reg = <0x0 0x0 0x0 0x100000>;
no-map;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@f0000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xf0800000 0 0x10000>, /* GICD */
<0x0 0xf0a00000 0 0x200000>, /* GICR */
<0x0 0xf0000000 0 0x2000>, /* GICC */
<0x0 0xf0010000 0 0x1000>, /* GICH */
<0x0 0xf0020000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pcie@fbd00000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
#interrupt-cells = <1>;
reg = <0x0 0xfbd00000 0x0 0x100000>;
interrupt-map-mask = <0xf800 0 0 7>;
/* 8 x legacy interrupts for SATA only */
interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
<0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
<0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
<0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
<0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
<0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
<0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
msi-parent = <&msix>;
};
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
interrupt-controller;
msi-controller;
al,msi-base-spi = <336>;
al,msi-num-spis = <959>;
interrupt-parent = <&gic>;
};
io-fabric {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xfc000000 0x2000000>;
uart0: serial@1883000 {
compatible = "ns16550a";
reg = <0x1883000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* Filled by firmware */
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@1884000 {
compatible = "ns16550a";
reg = <0x1884000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* Filled by firmware */
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@1885000 {
compatible = "ns16550a";
reg = <0x1885000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* Filled by firmware */
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@1886000 {
compatible = "ns16550a";
reg = <0x1886000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* Filled by firmware */
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
};
};
};