#ifndef ASIC_REG_NIC0_QM0_REGS_H_
#define ASIC_REG_NIC0_QM0_REGS_H_
#define mmNIC0_QM0_GLBL_CFG0 0xCE0000
#define mmNIC0_QM0_GLBL_CFG1 0xCE0004
#define mmNIC0_QM0_GLBL_PROT 0xCE0008
#define mmNIC0_QM0_GLBL_ERR_CFG 0xCE000C
#define mmNIC0_QM0_GLBL_SECURE_PROPS_0 0xCE0010
#define mmNIC0_QM0_GLBL_SECURE_PROPS_1 0xCE0014
#define mmNIC0_QM0_GLBL_SECURE_PROPS_2 0xCE0018
#define mmNIC0_QM0_GLBL_SECURE_PROPS_3 0xCE001C
#define mmNIC0_QM0_GLBL_SECURE_PROPS_4 0xCE0020
#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0 0xCE0024
#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1 0xCE0028
#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2 0xCE002C
#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3 0xCE0030
#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4 0xCE0034
#define mmNIC0_QM0_GLBL_STS0 0xCE0038
#define mmNIC0_QM0_GLBL_STS1_0 0xCE0040
#define mmNIC0_QM0_GLBL_STS1_1 0xCE0044
#define mmNIC0_QM0_GLBL_STS1_2 0xCE0048
#define mmNIC0_QM0_GLBL_STS1_3 0xCE004C
#define mmNIC0_QM0_GLBL_STS1_4 0xCE0050
#define mmNIC0_QM0_GLBL_MSG_EN_0 0xCE0054
#define mmNIC0_QM0_GLBL_MSG_EN_1 0xCE0058
#define mmNIC0_QM0_GLBL_MSG_EN_2 0xCE005C
#define mmNIC0_QM0_GLBL_MSG_EN_3 0xCE0060
#define mmNIC0_QM0_GLBL_MSG_EN_4 0xCE0068
#define mmNIC0_QM0_PQ_BASE_LO_0 0xCE0070
#define mmNIC0_QM0_PQ_BASE_LO_1 0xCE0074
#define mmNIC0_QM0_PQ_BASE_LO_2 0xCE0078
#define mmNIC0_QM0_PQ_BASE_LO_3 0xCE007C
#define mmNIC0_QM0_PQ_BASE_HI_0 0xCE0080
#define mmNIC0_QM0_PQ_BASE_HI_1 0xCE0084
#define mmNIC0_QM0_PQ_BASE_HI_2 0xCE0088
#define mmNIC0_QM0_PQ_BASE_HI_3 0xCE008C
#define mmNIC0_QM0_PQ_SIZE_0 0xCE0090
#define mmNIC0_QM0_PQ_SIZE_1 0xCE0094
#define mmNIC0_QM0_PQ_SIZE_2 0xCE0098
#define mmNIC0_QM0_PQ_SIZE_3 0xCE009C
#define mmNIC0_QM0_PQ_PI_0 0xCE00A0
#define mmNIC0_QM0_PQ_PI_1 0xCE00A4
#define mmNIC0_QM0_PQ_PI_2 0xCE00A8
#define mmNIC0_QM0_PQ_PI_3 0xCE00AC
#define mmNIC0_QM0_PQ_CI_0 0xCE00B0
#define mmNIC0_QM0_PQ_CI_1 0xCE00B4
#define mmNIC0_QM0_PQ_CI_2 0xCE00B8
#define mmNIC0_QM0_PQ_CI_3 0xCE00BC
#define mmNIC0_QM0_PQ_CFG0_0 0xCE00C0
#define mmNIC0_QM0_PQ_CFG0_1 0xCE00C4
#define mmNIC0_QM0_PQ_CFG0_2 0xCE00C8
#define mmNIC0_QM0_PQ_CFG0_3 0xCE00CC
#define mmNIC0_QM0_PQ_CFG1_0 0xCE00D0
#define mmNIC0_QM0_PQ_CFG1_1 0xCE00D4
#define mmNIC0_QM0_PQ_CFG1_2 0xCE00D8
#define mmNIC0_QM0_PQ_CFG1_3 0xCE00DC
#define mmNIC0_QM0_PQ_ARUSER_31_11_0 0xCE00E0
#define mmNIC0_QM0_PQ_ARUSER_31_11_1 0xCE00E4
#define mmNIC0_QM0_PQ_ARUSER_31_11_2 0xCE00E8
#define mmNIC0_QM0_PQ_ARUSER_31_11_3 0xCE00EC
#define mmNIC0_QM0_PQ_STS0_0 0xCE00F0
#define mmNIC0_QM0_PQ_STS0_1 0xCE00F4
#define mmNIC0_QM0_PQ_STS0_2 0xCE00F8
#define mmNIC0_QM0_PQ_STS0_3 0xCE00FC
#define mmNIC0_QM0_PQ_STS1_0 0xCE0100
#define mmNIC0_QM0_PQ_STS1_1 0xCE0104
#define mmNIC0_QM0_PQ_STS1_2 0xCE0108
#define mmNIC0_QM0_PQ_STS1_3 0xCE010C
#define mmNIC0_QM0_CQ_CFG0_0 0xCE0110
#define mmNIC0_QM0_CQ_CFG0_1 0xCE0114
#define mmNIC0_QM0_CQ_CFG0_2 0xCE0118
#define mmNIC0_QM0_CQ_CFG0_3 0xCE011C
#define mmNIC0_QM0_CQ_CFG0_4 0xCE0120
#define mmNIC0_QM0_CQ_CFG1_0 0xCE0124
#define mmNIC0_QM0_CQ_CFG1_1 0xCE0128
#define mmNIC0_QM0_CQ_CFG1_2 0xCE012C
#define mmNIC0_QM0_CQ_CFG1_3 0xCE0130
#define mmNIC0_QM0_CQ_CFG1_4 0xCE0134
#define mmNIC0_QM0_CQ_ARUSER_31_11_0 0xCE0138
#define mmNIC0_QM0_CQ_ARUSER_31_11_1 0xCE013C
#define mmNIC0_QM0_CQ_ARUSER_31_11_2 0xCE0140
#define mmNIC0_QM0_CQ_ARUSER_31_11_3 0xCE0144
#define mmNIC0_QM0_CQ_ARUSER_31_11_4 0xCE0148
#define mmNIC0_QM0_CQ_STS0_0 0xCE014C
#define mmNIC0_QM0_CQ_STS0_1 0xCE0150
#define mmNIC0_QM0_CQ_STS0_2 0xCE0154
#define mmNIC0_QM0_CQ_STS0_3 0xCE0158
#define mmNIC0_QM0_CQ_STS0_4 0xCE015C
#define mmNIC0_QM0_CQ_STS1_0 0xCE0160
#define mmNIC0_QM0_CQ_STS1_1 0xCE0164
#define mmNIC0_QM0_CQ_STS1_2 0xCE0168
#define mmNIC0_QM0_CQ_STS1_3 0xCE016C
#define mmNIC0_QM0_CQ_STS1_4 0xCE0170
#define mmNIC0_QM0_CQ_PTR_LO_0 0xCE0174
#define mmNIC0_QM0_CQ_PTR_HI_0 0xCE0178
#define mmNIC0_QM0_CQ_TSIZE_0 0xCE017C
#define mmNIC0_QM0_CQ_CTL_0 0xCE0180
#define mmNIC0_QM0_CQ_PTR_LO_1 0xCE0184
#define mmNIC0_QM0_CQ_PTR_HI_1 0xCE0188
#define mmNIC0_QM0_CQ_TSIZE_1 0xCE018C
#define mmNIC0_QM0_CQ_CTL_1 0xCE0190
#define mmNIC0_QM0_CQ_PTR_LO_2 0xCE0194
#define mmNIC0_QM0_CQ_PTR_HI_2 0xCE0198
#define mmNIC0_QM0_CQ_TSIZE_2 0xCE019C
#define mmNIC0_QM0_CQ_CTL_2 0xCE01A0
#define mmNIC0_QM0_CQ_PTR_LO_3 0xCE01A4
#define mmNIC0_QM0_CQ_PTR_HI_3 0xCE01A8
#define mmNIC0_QM0_CQ_TSIZE_3 0xCE01AC
#define mmNIC0_QM0_CQ_CTL_3 0xCE01B0
#define mmNIC0_QM0_CQ_PTR_LO_4 0xCE01B4
#define mmNIC0_QM0_CQ_PTR_HI_4 0xCE01B8
#define mmNIC0_QM0_CQ_TSIZE_4 0xCE01BC
#define mmNIC0_QM0_CQ_CTL_4 0xCE01C0
#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0xCE01C4
#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0xCE01C8
#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0xCE01CC
#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0xCE01D0
#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0xCE01D4
#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0xCE01D8
#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0xCE01DC
#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0xCE01E0
#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0xCE01E4
#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0xCE01E8
#define mmNIC0_QM0_CQ_TSIZE_STS_0 0xCE01EC
#define mmNIC0_QM0_CQ_TSIZE_STS_1 0xCE01F0
#define mmNIC0_QM0_CQ_TSIZE_STS_2 0xCE01F4
#define mmNIC0_QM0_CQ_TSIZE_STS_3 0xCE01F8
#define mmNIC0_QM0_CQ_TSIZE_STS_4 0xCE01FC
#define mmNIC0_QM0_CQ_CTL_STS_0 0xCE0200
#define mmNIC0_QM0_CQ_CTL_STS_1 0xCE0204
#define mmNIC0_QM0_CQ_CTL_STS_2 0xCE0208
#define mmNIC0_QM0_CQ_CTL_STS_3 0xCE020C
#define mmNIC0_QM0_CQ_CTL_STS_4 0xCE0210
#define mmNIC0_QM0_CQ_IFIFO_CNT_0 0xCE0214
#define mmNIC0_QM0_CQ_IFIFO_CNT_1 0xCE0218
#define mmNIC0_QM0_CQ_IFIFO_CNT_2 0xCE021C
#define mmNIC0_QM0_CQ_IFIFO_CNT_3 0xCE0220
#define mmNIC0_QM0_CQ_IFIFO_CNT_4 0xCE0224
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0xCE0228
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0xCE022C
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0xCE0230
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0xCE0234
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0xCE0238
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0xCE023C
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0xCE0240
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0xCE0244
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0xCE0248
#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0xCE024C
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0xCE0250
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0xCE0254
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0xCE0258
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0xCE025C
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0xCE0260
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0xCE0264
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0xCE0268
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0xCE026C
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0xCE0270
#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0xCE0274
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0xCE0278
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0xCE027C
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0xCE0280
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0xCE0284
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0xCE0288
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0xCE028C
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0xCE0290
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0xCE0294
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0xCE0298
#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0xCE029C
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0xCE02A0
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0xCE02A4
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0xCE02A8
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0xCE02AC
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0xCE02B0
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0xCE02B4
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0xCE02B8
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0xCE02BC
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0xCE02C0
#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0xCE02C4
#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 0xCE02C8
#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1 0xCE02CC
#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2 0xCE02D0
#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3 0xCE02D4
#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4 0xCE02D8
#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE02E0
#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE02E4
#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE02E8
#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE02EC
#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE02F0
#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE02F4
#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE02F8
#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE02FC
#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE0300
#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE0304
#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0xCE0308
#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0xCE030C
#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0xCE0310
#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0xCE0314
#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0xCE0318
#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0xCE031C
#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0xCE0320
#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0xCE0324
#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0xCE0328
#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0xCE032C
#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0xCE0330
#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0xCE0334
#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0xCE0338
#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0xCE033C
#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0xCE0340
#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0xCE0344
#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0xCE0348
#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0xCE034C
#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0xCE0350
#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0xCE0354
#define mmNIC0_QM0_CP_FENCE0_CNT_0 0xCE0358
#define mmNIC0_QM0_CP_FENCE0_CNT_1 0xCE035C
#define mmNIC0_QM0_CP_FENCE0_CNT_2 0xCE0360
#define mmNIC0_QM0_CP_FENCE0_CNT_3 0xCE0364
#define mmNIC0_QM0_CP_FENCE0_CNT_4 0xCE0368
#define mmNIC0_QM0_CP_FENCE1_CNT_0 0xCE036C
#define mmNIC0_QM0_CP_FENCE1_CNT_1 0xCE0370
#define mmNIC0_QM0_CP_FENCE1_CNT_2 0xCE0374
#define mmNIC0_QM0_CP_FENCE1_CNT_3 0xCE0378
#define mmNIC0_QM0_CP_FENCE1_CNT_4 0xCE037C
#define mmNIC0_QM0_CP_FENCE2_CNT_0 0xCE0380
#define mmNIC0_QM0_CP_FENCE2_CNT_1 0xCE0384
#define mmNIC0_QM0_CP_FENCE2_CNT_2 0xCE0388
#define mmNIC0_QM0_CP_FENCE2_CNT_3 0xCE038C
#define mmNIC0_QM0_CP_FENCE2_CNT_4 0xCE0390
#define mmNIC0_QM0_CP_FENCE3_CNT_0 0xCE0394
#define mmNIC0_QM0_CP_FENCE3_CNT_1 0xCE0398
#define mmNIC0_QM0_CP_FENCE3_CNT_2 0xCE039C
#define mmNIC0_QM0_CP_FENCE3_CNT_3 0xCE03A0
#define mmNIC0_QM0_CP_FENCE3_CNT_4 0xCE03A4
#define mmNIC0_QM0_CP_STS_0 0xCE03A8
#define mmNIC0_QM0_CP_STS_1 0xCE03AC
#define mmNIC0_QM0_CP_STS_2 0xCE03B0
#define mmNIC0_QM0_CP_STS_3 0xCE03B4
#define mmNIC0_QM0_CP_STS_4 0xCE03B8
#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0xCE03BC
#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0xCE03C0
#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0xCE03C4
#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0xCE03C8
#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0xCE03CC
#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0xCE03D0
#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0xCE03D4
#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0xCE03D8
#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0xCE03DC
#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0xCE03E0
#define mmNIC0_QM0_CP_BARRIER_CFG_0 0xCE03F4
#define mmNIC0_QM0_CP_BARRIER_CFG_1 0xCE03F8
#define mmNIC0_QM0_CP_BARRIER_CFG_2 0xCE03FC
#define mmNIC0_QM0_CP_BARRIER_CFG_3 0xCE0400
#define mmNIC0_QM0_CP_BARRIER_CFG_4 0xCE0404
#define mmNIC0_QM0_CP_DBG_0_0 0xCE0408
#define mmNIC0_QM0_CP_DBG_0_1 0xCE040C
#define mmNIC0_QM0_CP_DBG_0_2 0xCE0410
#define mmNIC0_QM0_CP_DBG_0_3 0xCE0414
#define mmNIC0_QM0_CP_DBG_0_4 0xCE0418
#define mmNIC0_QM0_CP_ARUSER_31_11_0 0xCE041C
#define mmNIC0_QM0_CP_ARUSER_31_11_1 0xCE0420
#define mmNIC0_QM0_CP_ARUSER_31_11_2 0xCE0424
#define mmNIC0_QM0_CP_ARUSER_31_11_3 0xCE0428
#define mmNIC0_QM0_CP_ARUSER_31_11_4 0xCE042C
#define mmNIC0_QM0_CP_AWUSER_31_11_0 0xCE0430
#define mmNIC0_QM0_CP_AWUSER_31_11_1 0xCE0434
#define mmNIC0_QM0_CP_AWUSER_31_11_2 0xCE0438
#define mmNIC0_QM0_CP_AWUSER_31_11_3 0xCE043C
#define mmNIC0_QM0_CP_AWUSER_31_11_4 0xCE0440
#define mmNIC0_QM0_ARB_CFG_0 0xCE0A00
#define mmNIC0_QM0_ARB_CHOISE_Q_PUSH 0xCE0A04
#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0xCE0A08
#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0xCE0A0C
#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0xCE0A10
#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0xCE0A14
#define mmNIC0_QM0_ARB_CFG_1 0xCE0A18
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0xCE0A20
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0xCE0A24
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0xCE0A28
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0xCE0A2C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0xCE0A30
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0xCE0A34
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0xCE0A38
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0xCE0A3C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0xCE0A40
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0xCE0A44
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0xCE0A48
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0xCE0A4C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0xCE0A50
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0xCE0A54
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0xCE0A58
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0xCE0A5C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0xCE0A60
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0xCE0A64
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0xCE0A68
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0xCE0A6C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0xCE0A70
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0xCE0A74
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0xCE0A78
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0xCE0A7C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0xCE0A80
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0xCE0A84
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0xCE0A88
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0xCE0A8C
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0xCE0A90
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0xCE0A94
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0xCE0A98
#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0xCE0A9C
#define mmNIC0_QM0_ARB_MST_CRED_INC 0xCE0AA0
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xCE0AA4
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xCE0AA8
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xCE0AAC
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xCE0AB0
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xCE0AB4
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xCE0AB8
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xCE0ABC
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xCE0AC0
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xCE0AC4
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xCE0AC8
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xCE0ACC
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xCE0AD0
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xCE0AD4
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xCE0AD8
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xCE0ADC
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xCE0AE0
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xCE0AE4
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xCE0AE8
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xCE0AEC
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xCE0AF0
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xCE0AF4
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xCE0AF8
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xCE0AFC
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xCE0B00
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xCE0B04
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xCE0B08
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xCE0B0C
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xCE0B10
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xCE0B14
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xCE0B18
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xCE0B1C
#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xCE0B20
#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xCE0B28
#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0xCE0B2C
#define mmNIC0_QM0_ARB_MST_QUIET_PER 0xCE0B34
#define mmNIC0_QM0_ARB_SLV_CHOISE_WDT 0xCE0B38
#define mmNIC0_QM0_ARB_SLV_ID 0xCE0B3C
#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0xCE0B44
#define mmNIC0_QM0_ARB_MSG_AWUSER_31_11 0xCE0B48
#define mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP 0xCE0B4C
#define mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE0B50
#define mmNIC0_QM0_ARB_BASE_LO 0xCE0B54
#define mmNIC0_QM0_ARB_BASE_HI 0xCE0B58
#define mmNIC0_QM0_ARB_STATE_STS 0xCE0B80
#define mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS 0xCE0B84
#define mmNIC0_QM0_ARB_MSG_STS 0xCE0B88
#define mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD 0xCE0B8C
#define mmNIC0_QM0_ARB_ERR_CAUSE 0xCE0B9C
#define mmNIC0_QM0_ARB_ERR_MSG_EN 0xCE0BA0
#define mmNIC0_QM0_ARB_ERR_STS_DRP 0xCE0BA8
#define mmNIC0_QM0_ARB_MST_CRED_STS_0 0xCE0BB0
#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0xCE0BB4
#define mmNIC0_QM0_ARB_MST_CRED_STS_2 0xCE0BB8
#define mmNIC0_QM0_ARB_MST_CRED_STS_3 0xCE0BBC
#define mmNIC0_QM0_ARB_MST_CRED_STS_4 0xCE0BC0
#define mmNIC0_QM0_ARB_MST_CRED_STS_5 0xCE0BC4
#define mmNIC0_QM0_ARB_MST_CRED_STS_6 0xCE0BC8
#define mmNIC0_QM0_ARB_MST_CRED_STS_7 0xCE0BCC
#define mmNIC0_QM0_ARB_MST_CRED_STS_8 0xCE0BD0
#define mmNIC0_QM0_ARB_MST_CRED_STS_9 0xCE0BD4
#define mmNIC0_QM0_ARB_MST_CRED_STS_10 0xCE0BD8
#define mmNIC0_QM0_ARB_MST_CRED_STS_11 0xCE0BDC
#define mmNIC0_QM0_ARB_MST_CRED_STS_12 0xCE0BE0
#define mmNIC0_QM0_ARB_MST_CRED_STS_13 0xCE0BE4
#define mmNIC0_QM0_ARB_MST_CRED_STS_14 0xCE0BE8
#define mmNIC0_QM0_ARB_MST_CRED_STS_15 0xCE0BEC
#define mmNIC0_QM0_ARB_MST_CRED_STS_16 0xCE0BF0
#define mmNIC0_QM0_ARB_MST_CRED_STS_17 0xCE0BF4
#define mmNIC0_QM0_ARB_MST_CRED_STS_18 0xCE0BF8
#define mmNIC0_QM0_ARB_MST_CRED_STS_19 0xCE0BFC
#define mmNIC0_QM0_ARB_MST_CRED_STS_20 0xCE0C00
#define mmNIC0_QM0_ARB_MST_CRED_STS_21 0xCE0C04
#define mmNIC0_QM0_ARB_MST_CRED_STS_22 0xCE0C08
#define mmNIC0_QM0_ARB_MST_CRED_STS_23 0xCE0C0C
#define mmNIC0_QM0_ARB_MST_CRED_STS_24 0xCE0C10
#define mmNIC0_QM0_ARB_MST_CRED_STS_25 0xCE0C14
#define mmNIC0_QM0_ARB_MST_CRED_STS_26 0xCE0C18
#define mmNIC0_QM0_ARB_MST_CRED_STS_27 0xCE0C1C
#define mmNIC0_QM0_ARB_MST_CRED_STS_28 0xCE0C20
#define mmNIC0_QM0_ARB_MST_CRED_STS_29 0xCE0C24
#define mmNIC0_QM0_ARB_MST_CRED_STS_30 0xCE0C28
#define mmNIC0_QM0_ARB_MST_CRED_STS_31 0xCE0C2C
#define mmNIC0_QM0_CGM_CFG 0xCE0C70
#define mmNIC0_QM0_CGM_STS 0xCE0C74
#define mmNIC0_QM0_CGM_CFG1 0xCE0C78
#define mmNIC0_QM0_LOCAL_RANGE_BASE 0xCE0C80
#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0xCE0C84
#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0xCE0C90
#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0xCE0C94
#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0xCE0C98
#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0xCE0C9C
#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0xCE0CA0
#define mmNIC0_QM0_GLBL_AXCACHE 0xCE0CA4
#define mmNIC0_QM0_IND_GW_APB_CFG 0xCE0CB0
#define mmNIC0_QM0_IND_GW_APB_WDATA 0xCE0CB4
#define mmNIC0_QM0_IND_GW_APB_RDATA 0xCE0CB8
#define mmNIC0_QM0_IND_GW_APB_STATUS 0xCE0CBC
#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0xCE0CD0
#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0xCE0CD4
#define mmNIC0_QM0_GLBL_ERR_WDATA 0xCE0CD8
#define mmNIC0_QM0_GLBL_MEM_INIT_BUSY 0xCE0D00
#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */