#ifndef ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_
#define ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_ASID 0x4C8AB80
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP 0x4C8AB84
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_STRONG_ORDER 0x4C8AB88
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_NO_SNOOP 0x4C8AB8C
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_REDUCTION 0x4C8AB90
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_ATOMIC 0x4C8AB94
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_QOS 0x4C8AB98
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RSVD 0x4C8AB9C
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE 0x4C8ABA0
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_CORE 0x4C8ABA4
#define mmPDMA0_QM_AXUSER_NONSECURED_E2E_COORD 0x4C8ABA8
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO 0x4C8ABB0
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI 0x4C8ABB4
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO 0x4C8ABB8
#define mmPDMA0_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI 0x4C8ABBC
#define mmPDMA0_QM_AXUSER_NONSECURED_LB_COORD 0x4C8ABC0
#define mmPDMA0_QM_AXUSER_NONSECURED_LB_LOCK 0x4C8ABC4
#define mmPDMA0_QM_AXUSER_NONSECURED_LB_RSVD 0x4C8ABC8
#define mmPDMA0_QM_AXUSER_NONSECURED_LB_OVRD 0x4C8ABCC
#endif /* ASIC_REG_PDMA0_QM_AXUSER_NONSECURED_REGS_H_ */