# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright 2019 BayLibre, SAS %YAML 1.2 --- $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson DWMAC Ethernet controller maintainers: - Neil Armstrong <neil.armstrong@linaro.org> - Martin Blumenstingl <martin.blumenstingl@googlemail.com> # We need a select here so we don't match all nodes with 'snps,dwmac' select: properties: compatible: contains: enum: - amlogic,meson6-dwmac - amlogic,meson8b-dwmac - amlogic,meson8m2-dwmac - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac required: - compatible allOf: - $ref: snps,dwmac.yaml# - if: properties: compatible: contains: enum: - amlogic,meson8b-dwmac - amlogic,meson8m2-dwmac - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac then: properties: clocks: minItems: 3 items: - description: GMAC main clock - description: First parent clock of the internal mux - description: Second parent clock of the internal mux - description: The clock which drives the timing adjustment logic clock-names: minItems: 3 items: - const: stmmaceth - const: clkin0 - const: clkin1 - const: timing-adjustment amlogic,tx-delay-ns: $ref: /schemas/types.yaml#/definitions/uint32 description: The internal RGMII TX clock delay (provided by this driver) in nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns. When phy-mode is set to "rgmii" then the TX delay should be explicitly configured. When not configured a fallback of 2ns is used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid" the TX clock delay is already provided by the PHY. In that case this property should be set to 0ns (which disables the TX clock delay in the MAC to prevent the clock from going off because both PHY and MAC are adding a delay). Any configuration is ignored when the phy-mode is set to "rmii". amlogic,rx-delay-ns: deprecated: true enum: - 0 - 2 default: 0 description: The internal RGMII RX clock delay in nanoseconds. Deprecated, use rx-internal-delay-ps instead. rx-internal-delay-ps: default: 0 - if: properties: compatible: contains: enum: - amlogic,meson8b-dwmac - amlogic,meson8m2-dwmac - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac then: properties: rx-internal-delay-ps: enum: - 0 - 2000 - if: properties: compatible: contains: enum: - amlogic,meson-g12a-dwmac then: properties: rx-internal-delay-ps: enum: - 0 - 200 - 400 - 600 - 800 - 1000 - 1200 - 1400 - 1600 - 1800 - 2000 - 2200 - 2400 - 2600 - 2800 - 3000 properties: compatible: additionalItems: true maxItems: 3 items: - enum: - amlogic,meson6-dwmac - amlogic,meson8b-dwmac - amlogic,meson8m2-dwmac - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac contains: enum: - snps,dwmac-3.70a - snps,dwmac reg: items: - description: The first register range should be the one of the DWMAC controller - description: The second range is is for the Amlogic specific configuration (for example the PRG_ETHERNET register range on Meson8b and newer) required: - compatible - reg - interrupts - interrupt-names - clocks - clock-names - phy-mode unevaluatedProperties: false examples: - | ethmac: ethernet@c9410000 { compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000>, <0xc8834540 0x8>; interrupts = <8>; interrupt-names = "macirq"; clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>; clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; phy-mode = "rgmii"; };