Symbol: r0

macro public

Defined...

• drivers/block/paride/paride.h:105:9-105:48: #define r0() (in_p(0) & 0xff)

function parameter

Defined...

• crypto/serpent_generic.c:233:44-233:48: static noinline void __serpent_setkey_sbox(u32 r0, u32 r1, u32 r2,

variable

Defined...

• crypto/serpent_generic.c:279:2-279:6: u32 r0, r1, r2, r3, r4;
• crypto/serpent_generic.c:458:2-458:6: u32 r0, r1, r2, r3, r4;
• crypto/serpent_generic.c:524:2-524:6: u32 r0, r1, r2, r3, r4;
• crypto/streebog_generic.c:869:2-869:6: u64 r0, r1, r2, r3, r4, r5, r6, r7;
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:105:2-105:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:106:2-106:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:255:3-255:3: WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:261:2-261:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:290:3-290:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:292:3-292:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:294:3-294:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:296:3-296:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:303:2-303:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:308:2-308:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:560:3-560:3: WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:574:2-574:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:5010:3-5010:3: WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:5012:3-5012:3: WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:5014:3-5014:3: WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:5631:3-5631:3: WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1998:2-1998:2: WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2010:2-2010:2: WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2497:3-2497:3: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2498:3-2498:3: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2552:2-2552:2: WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2571:4-2571:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2572:4-2572:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2578:4-2578:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2583:4-2583:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2657:2-2657:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2659:2-2659:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2661:2-2661:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3127:2-3127:2: WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3323:3-3323:3: WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3325:3-3325:3: WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3384:2-3384:2: WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3386:2-3386:2: WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3562:2-3562:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3564:2-3564:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3568:2-3568:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3572:2-3572:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3577:3-3577:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3583:3-3583:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3585:3-3585:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3587:3-3587:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3589:3-3589:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3594:2-3594:2: WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3596:2-3596:2: WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3600:2-3600:2: WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3604:2-3604:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3606:2-3606:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3610:2-3610:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3614:2-3614:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3616:2-3616:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3620:2-3620:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3622:2-3622:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3633:2-3633:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3637:2-3637:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3639:2-3639:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3643:2-3643:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3645:2-3645:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3649:2-3649:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3666:3-3666:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3678:4-3678:4: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3681:3-3681:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3685:2-3685:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3686:2-3686:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3687:2-3687:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3688:2-3688:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3689:2-3689:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3690:2-3690:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3691:2-3691:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3692:2-3692:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:76:2-76:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:77:2-77:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:78:2-78:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:82:3-82:3: WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:93:4-93:4: WREG32_SOC15_RLC(GC, 0,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:98:4-98:4: WREG32_SOC15_RLC(
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:139:2-139:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:156:2-156:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:161:2-161:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:173:2-173:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:178:2-178:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:287:3-287:3: WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:289:3-289:3: WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:327:2-327:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/soc15.c:420:4-420:4: WREG32_RLC(reg, tmp);
• drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c:509:2-509:6: u32 r0, r4, rt, rblock_size;
• drivers/media/dvb-frontends/stv090x.c:1655:2-1655:17: u8 r3, r2, r1, r0;
• drivers/mmc/host/s3cmci.c:148:2-148:40: u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer;
• drivers/net/ethernet/freescale/enetc/enetc_qos.c:263:3-263:15: u32 m0, ma, r0, ra;
• drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c:3002:2-3002:6: u32 r0, r1, r2;
• drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:624:2-624:11: int err, r0, r1;
• drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:709:2-709:11: int err, r0, r1;
• drivers/pinctrl/mediatek/pinctrl-paris.c:582:2-582:54: int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1;
• drivers/scsi/pm8001/pm80xx_hwi.c:1545:4-1545:57: u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
• kernel/bpf/verifier.c:4890:2-4890:24: struct bpf_reg_state *r0;
• lib/crypto/curve25519-hacl64.c:93:3-93:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:102:3-102:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:112:3-112:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:121:3-121:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:220:2-220:19: u64 r0 = output[0];
• lib/crypto/poly1305-donna64.c:39:2-39:6: u64 r0, r1, r2;
• sound/soc/codecs/rt1011.c:2169:2-2169:37: unsigned int value, count = 0, r0[3];

variable local

Defined...

• kernel/resource_kunit.c:22:1-22:64: static struct resource r0 = { .start = R0_START, .end = R0_END };