Symbol: r0

macro public

Defined...

• drivers/block/paride/paride.h:105:9-105:48: #define r0() (in_p(0) & 0xff)

function parameter

Defined...

• crypto/serpent_generic.c:233:44-233:48: static noinline void __serpent_setkey_sbox(u32 r0, u32 r1, u32 r2,

variable

Defined...

• crypto/serpent_generic.c:279:2-279:6: u32 r0, r1, r2, r3, r4;
• crypto/serpent_generic.c:458:2-458:6: u32 r0, r1, r2, r3, r4;
• crypto/serpent_generic.c:524:2-524:6: u32 r0, r1, r2, r3, r4;
• crypto/streebog_generic.c:869:2-869:6: u64 r0, r1, r2, r3, r4, r5, r6, r7;
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:106:2-106:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:107:2-107:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:256:3-256:3: WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:262:2-262:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:291:3-291:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:293:3-293:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:295:3-295:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:297:3-297:3: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:304:2-304:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:309:2-309:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:561:3-561:3: WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
• drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:575:2-575:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:4776:3-4776:3: WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:4778:3-4778:3: WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:4780:3-4780:3: WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
• drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:5397:3-5397:3: WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1987:2-1987:2: WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:1999:2-1999:2: WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2489:3-2489:3: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2490:3-2490:3: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2544:2-2544:2: WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2563:4-2563:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2564:4-2564:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2570:4-2570:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2575:4-2575:4: WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2642:2-2642:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2644:2-2644:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:2646:2-2646:2: WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3112:2-3112:2: WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3308:3-3308:3: WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3310:3-3310:3: WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3369:2-3369:2: WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3371:2-3371:2: WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3545:2-3545:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3547:2-3547:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3551:2-3551:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3555:2-3555:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3560:3-3560:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3566:3-3566:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3568:3-3568:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3570:3-3570:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3572:3-3572:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3577:2-3577:2: WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3579:2-3579:2: WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3583:2-3583:2: WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3587:2-3587:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3589:2-3589:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3593:2-3593:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3597:2-3597:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3599:2-3599:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3603:2-3603:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3605:2-3605:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3616:2-3616:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3620:2-3620:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3622:2-3622:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3626:2-3626:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3628:2-3628:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3632:2-3632:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3649:3-3649:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3661:4-3661:4: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3664:3-3664:3: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3668:2-3668:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3669:2-3669:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3670:2-3670:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3671:2-3671:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3672:2-3672:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3673:2-3673:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3674:2-3674:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
• drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3675:2-3675:2: WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:74:2-74:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:75:2-75:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:76:2-76:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:80:3-80:3: WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:91:4-91:4: WREG32_SOC15_RLC(GC, 0,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:96:4-96:4: WREG32_SOC15_RLC(
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:137:2-137:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:154:2-154:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:159:2-159:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:171:2-171:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:176:2-176:2: WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:285:3-285:3: WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:287:3-287:3: WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
• drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c:325:2-325:2: WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
• drivers/gpu/drm/amd/amdgpu/soc15.c:467:4-467:4: WREG32_RLC(reg, tmp);
• drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c:510:2-510:6: u32 r0, r4, rt, rblock_size;
• drivers/media/dvb-frontends/stv090x.c:1655:2-1655:17: u8 r3, r2, r1, r0;
• drivers/net/ethernet/freescale/enetc/enetc_qos.c:276:3-276:15: u32 m0, ma, r0, ra;
• drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:621:2-621:11: int err, r0, r1;
• drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:706:2-706:11: int err, r0, r1;
• drivers/pinctrl/mediatek/pinctrl-paris.c:582:2-582:54: int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1;
• drivers/scsi/pm8001/pm80xx_hwi.c:1573:4-1573:57: u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
• kernel/bpf/verifier.c:4596:2-4596:24: struct bpf_reg_state *r0;
• lib/crypto/curve25519-hacl64.c:93:3-93:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:102:3-102:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:112:3-112:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:121:3-121:28: u64 r0 = ((u64)(tctr)) & 0x7ffffffffffffLLU;
• lib/crypto/curve25519-hacl64.c:220:2-220:19: u64 r0 = output[0];
• lib/crypto/poly1305-donna64.c:39:2-39:6: u64 r0, r1, r2;
• sound/soc/codecs/rt1011.c:2169:2-2169:37: unsigned int value, count = 0, r0[3];